Oxide tunneling current in metal oxide semiconductor (MOS) field effect transistors (FET) is a non-negligible component of power consumption as gate oxides get thinner, and may in the future become the dominant leakage mechanism in sub-100 nm complementary MOS (CMOS) circuits. The gate current is dependent on various conditions for a single transistor. There are three main static regions of operation for a MOSFET, and the amount of gate-leakage current differs by several orders of magnitude for each region. Whether a transistor leaks significantly is also affected by its position in relation to other transistors within a CMOS circuit because a transistor's position affects the voltage stress to which the transistor is subjected.
The three regions of operation are a function of applied bias if one only considers the parameters that affect the magnitude of gate current in a MOSFET as it operates in relation to other MOSFETs. Assuming that the supply voltage (Vdd) and the threshold voltage (Vt) are fixed, then a MOSFET in a static CMOS logic gate operates in one of three regions, each with a significantly different amount of gate leakage.
The first region of operation is called “strong inversion” and is the region in which a MOSFET operates with the absolute value of the gate to source voltage (|VGS|) equal to Vdd. The gate-leakage current density for an N-channel FET (NFET) in strong inversion may be as high as 1000 amperes per square centimeter (A/cm2) for an oxide thickness of 1.5 nanometers (nm) at Vdd equal to 3 volts (V). For such a thin oxide, a more realistic value for Vdd is 1.2 V, in which case the gate-leakage current would more likely be 20 A/cm2.
The second region of operation is called the “threshold” region in which |VGS|=Vt. A MOSFET operating in the threshold region will leak significantly less than a MOSFET operating in the strong inversion region—typically 3 to 6 orders of magnitude less, depending on Vdd and the oxide thickness.
The third region is called the “OFF” region where |VGS|=0.0 V. For an NFET operating in the OFF region, there is no leakage if the drain voltage (Vd)=0.0 V. However, if Vd is equal to Vdd, then a small leakage current in the reverse direction (drain to gate) may be present due to the gate-drain overlap area. This leakage current depends on transistor geometry and is typically 10 orders of magnitude less than the gate-leakage current in the strong inversion region.
The above three regions of operation represent three distinct conditions or states for the channel of a MOSFET. Whether an “ON” transistor operates at strong inversion or at threshold is determined by its position inside a logic circuit structure as well as by the state of other transistors in the circuit.
Both N-channel FETS (NFETS) and P-channel FETs (PFETs) operate in one of the three regions described above. However, the main tunneling current in a PFET device in strong inversion is due to hole tunneling from the valence band. On the other hand, the main tunneling current in an NFET device in strong inversion is due to electron tunneling from the conduction band. Therefore, PFET gate currents are about 10 times smaller than equivalently sized NFET devices. This size difference is important in assessing gate-leakage in a static CMOS circuit.
Since gate leakage currents are measured as current density, it follows that the gate-leakage current in a MOSFET is directly proportional to the gate area (width times length). Therefore, transistor sizing has a direct impact on the amount of gate-leakage in a CMOS logic circuit.
As CMOS circuits become smaller, leakage current that results when voltage is applied to the gate of a FET becomes a significant portion of the power dissipation. Leakage power may become the limiting factor in how small devices may be manufactured. As devices are made smaller, the power supply voltage is correspondingly reduced. However, reducing power supply voltage may not achieve an adequate reduction in leakage power dissipation. Alternate techniques may be employed to reduce leakage power. One popular technique is to use power-gating to isolate the power supply voltage in groups of circuits at controlled times. These circuits are sometimes referred to as being part of a power-gated domain. Other circuits may be evaluating a logic function and may not be in a power-gated domain. Interfacing between circuits in a power-gated domain and circuits in a non-power-gated domain may prove difficult. The state of an output from a power-gated domain may be uncertain during the time period of power-gating. While many benefits of power-gating are known, there is no consensus on strategies to preserve logic states of outputs in the power-gated domains. Since power-gated domains may be variable, the method of preserving output logic states from circuits in a power-gated domain are controlled by the power-gating control signals themselves.
A CMOS buffer's capability to drive current depends on the channel size of devices used to drive outputs or to drive many other logic gate inputs. Therefore, one would expect the large devices to exhibit large gate-leakage current when the technology has gate oxides that are very thin. Likewise, circuit regions with a high number of logic gates may exhibit a large gate-leakage current due to the large number of devices that are in strong inversion (between clock transitions). Logic regions with a high number of logic gates may employ power supply gating whereby the power to the logic devices are decoupled by the action of MOSFETs or PFETs for the positive power supply voltage and decoupled by the action of NFETs for the negative power supply voltage. These regions where power supply gating is employed are sometimes referred to as “cuttable” regions. When a cuttable region is interfaced with a non-cuttable region, then logic states at the interface outputs may become indeterminate when power is decoupled.
By providing feedback from the output of a power-gated or cuttable circuit, the circuit can be automatically power-gated after the output logic state has been established. This may be done by gating the stage that provides the drive to the power-gated output device with the proper phase of the output. To reduce leakage, sometimes it is desirable to control the time from when a logic state is asserted on the output until power-gating is activated. Allowing time between the assertion of an output logic state and power-gating enables the use of smaller device sizes. Some power-gating control circuits rely on elements within the control circuits to collapse from leakage through control circuit elements. In some instances, it may be desirable to turn off the drive stage more quickly, without waiting for control circuit elements to collapse through leakage.
Therefore, there is a need for a circuit design for low leakage circuits that enables automatic decoupling of leakage stressed devices quickly, without waiting on control circuits to collapse through leakage.